diff options
| author | Fabrizio Castro <fabrizio.castro@bp.renesas.com> | 2017-09-13 18:05:35 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-09-19 11:20:19 +0200 |
| commit | 7079131ef9b934df48602b22e30282d25a6a4827 (patch) | |
| tree | a931cb3255b58e410b39058769c3d9c6cddd356b /arch/arm/boot/dts/r8a7745.dtsi | |
| parent | 615beb759ca494a4b1a202f571af41549064dc2f (diff) | |
ARM: dts: r8a7745: Add SDHI controllers
Add the SDHI controllers to the r8a7745 device tree.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7745.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7745.dtsi | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 6e82991b7997..adf30890cb07 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -735,6 +735,48 @@ max-frequency = <97500000>; status = "disabled"; }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7745"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7745"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7745"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; }; /* External root clock */ |