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authorGeert Uytterhoeven <geert+renesas@glider.be>2017-08-18 11:11:36 +0200
committerSimon Horman <horms+renesas@verge.net.au>2017-09-18 08:05:04 +0200
commit762dbc444ca240580f7eda5b9152d147cca608b3 (patch)
tree1045ceeb34cca020a598ff8bb3fa4768c202d582 /arch/arm/boot/dts/r8a7792-blanche.dts
parent5802c420636559ffd37095d2886f6964d9b55b11 (diff)
ARM: dts: r8a7792: Convert to new CPG/MSSR bindings
Convert the R-Car V2H SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)" and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7792-blanche.dts')
-rw-r--r--arch/arm/boot/dts/r8a7792-blanche.dts3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
index f3ea43b7b724..9b67dca6c9ef 100644
--- a/arch/arm/boot/dts/r8a7792-blanche.dts
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -310,8 +310,7 @@
pinctrl-0 = <&du0_pins &du1_pins>;
pinctrl-names = "default";
- clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>,
- <&x1_clk>, <&x2_clk>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
status = "okay";