diff options
| author | Simon Horman <horms+renesas@verge.net.au> | 2017-12-18 22:32:33 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-12-20 12:52:33 +0100 |
| commit | 3da25909eadbc5ae8dcdec77b19dd1c893d64813 (patch) | |
| tree | 0d7e3f1d6bd0c7e37322899a69d6e834386b3a83 /arch/arm/boot/dts/r8a7792.dtsi | |
| parent | c3d2c8d7c20e9702acead1490dd278768ce333c4 (diff) | |
ARM: dts: r8a7792: move timer node out of bus
The timer node does not have any register properties and thus shouldn't be
placed on the bus.
This problem is flagged by the compiler as follows:
$ make dtbs W=1
...
DTC arch/arm/boot/dts/r8a7792-wheat.dtb
arch/arm/boot/dts/r8a7792-blanche.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
arch/arm/boot/dts/r8a7792-wheat.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm/boot/dts/r8a7792.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7792.dtsi | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index b0013e5fcf47..fa3f848dc368 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -137,18 +137,6 @@ resets = <&cpg 407>; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_LOW)>; - }; - rst: reset-controller@e6160000 { compatible = "renesas,r8a7792-rst"; reg = <0 0xe6160000 0 0x0100>; @@ -856,4 +844,12 @@ #power-domain-cells = <0>; }; }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; }; |