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authorDinh Nguyen <dinguyen@kernel.org>2018-09-10 09:12:08 -0500
committerDinh Nguyen <dinguyen@kernel.org>2018-09-17 10:11:28 -0500
commit20373e0cb8f7d540ae082a8026f5ae7c27cc6cb3 (patch)
tree525331e96d92f85e0165157e6a18952e16d49ef8 /arch/arm/boot/dts/socfpga.dtsi
parentcbbc488ed85061a765cf370c3e41f383c1e0add6 (diff)
ARM: dts: socfpga: add timer resets for SoCFPGA platform
Add the resets property for all the timers on the Cyclone5/Arria5/Arria10 platforms. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index daf249e57b08..b3ff5a86efdb 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -849,6 +849,8 @@
reg = <0xffc08000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
+ resets = <&rst SPTIMER0_RESET>;
+ reset-names = "timer";
};
timer1: timer1@ffc09000 {
@@ -857,6 +859,8 @@
reg = <0xffc09000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
+ resets = <&rst SPTIMER1_RESET>;
+ reset-names = "timer";
};
timer2: timer2@ffd00000 {
@@ -865,6 +869,8 @@
reg = <0xffd00000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
+ resets = <&rst OSC1TIMER0_RESET>;
+ reset-names = "timer";
};
timer3: timer3@ffd01000 {
@@ -873,6 +879,8 @@
reg = <0xffd01000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
+ resets = <&rst OSC1TIMER1_RESET>;
+ reset-names = "timer";
};
uart0: serial0@ffc02000 {