diff options
author | Dinh Nguyen <dinguyen@kernel.org> | 2020-07-31 10:26:40 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-09-17 13:47:41 +0200 |
commit | 6a2be713c78f0672da5f44ed88abfd42999133cd (patch) | |
tree | 34f1e7eb677e11f6d3f7ef795340e4edae8fed7c /arch/arm/boot/dts/socfpga_arria10.dtsi | |
parent | 25915590865ceee0d054d648921f553403a004d9 (diff) |
ARM: dts: socfpga: fix register entry for timer3 on Arria10
[ Upstream commit 0ff5a4812be4ebd4782bbb555d369636eea164f7 ]
Fixes the register address for the timer3 entry on Arria10.
Fixes: 475dc86d08de4 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
-rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 906bfb580e9e..f261a3344071 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -819,7 +819,7 @@ timer3: timer3@ffd00100 { compatible = "snps,dw-apb-timer"; interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd01000 0x100>; + reg = <0xffd00100 0x100>; clocks = <&l4_sys_free_clk>; clock-names = "timer"; resets = <&rst L4SYSTIMER1_RESET>; |