diff options
| author | Thor Thayer <tthayer@opensource.altera.com> | 2016-06-02 17:52:25 +0000 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@opensource.altera.com> | 2016-10-18 22:17:51 -0500 |
| commit | f2d6f8f8178142519c5b576582bec5cf9eabbaaf (patch) | |
| tree | 559e20a5d843a66441437b46227cf6329f5f6d6a /arch/arm/boot/dts/socfpga_arria10.dtsi | |
| parent | ecba2390e350cdce2c47800cde34d0fe91b53870 (diff) | |
ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip
Add the Altera Arria10 SPI Master Node in preparation for
the A10SR MFD node.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index ac0e19ca14b0..1149216c78c5 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -562,6 +562,21 @@ status = "disabled"; }; + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x100>; + interrupts = <0 102 4>; + num-chipselect = <4>; + bus-num = <0>; + /*32bit_access;*/ + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + sdr: sdr@ffc25000 { compatible = "syscon"; reg = <0xffcfb100 0x80>; |