summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/sun5i-a10s.dtsi
diff options
context:
space:
mode:
authorMaxime Ripard <maxime.ripard@bootlin.com>2018-11-07 10:58:01 +0100
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-11-28 11:37:08 +0100
commit6a9951a18b013b81759f11fd0d30fa5574d30bb6 (patch)
tree771134fe778fc612ef45c8c9ec5e4b9864f8e10e /arch/arm/boot/dts/sun5i-a10s.dtsi
parent79badc748b44ca0fa5ba51e11a4366953d624218 (diff)
ARM: dts: sun5i: Change pinctrl nodes to avoid warning
All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm/boot/dts/sun5i-a10s.dtsi')
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 195a6a1d2c49..7b44a227ba60 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -124,17 +124,17 @@
&pio {
compatible = "allwinner,sun5i-a10s-pinctrl";
- uart0_pins_a: uart0@0 {
+ uart0_pb_pins: uart0-pb-pins {
pins = "PB19", "PB20";
function = "uart0";
};
- uart2_pins_b: uart2@1 {
+ uart2_pc_pins: uart2-pc-pins {
pins = "PC18", "PC19";
function = "uart2";
};
- emac_pins_b: emac0@1 {
+ emac_pa_pins: emac-pa-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA9", "PA10",
@@ -143,19 +143,19 @@
function = "emac";
};
- mmc1_pins_a: mmc1@0 {
+ mmc1_pins: mmc1-pins {
pins = "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8";
function = "mmc1";
drive-strength = <30>;
};
- spi2_pins_b: spi2@1 {
+ spi2_pb_pins: spi2-pb-pins {
pins = "PB12", "PB13", "PB14";
function = "spi2";
};
- spi2_cs0_pins_b: spi2_cs0@1 {
+ spi2_cs0_pb_pin: spi2-cs0-pb-pin {
pins = "PB11";
function = "spi2";
};