diff options
| author | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-04-16 10:57:44 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-04-17 16:56:42 +0200 |
| commit | 66dc4e4bfc0b3ce8b6cb14d31c3676b5dde623cf (patch) | |
| tree | b4b988922dd13aac31d757ef4159d82b714dd8b7 /arch/arm/boot/dts/sun5i.dtsi | |
| parent | 4b03e16d3013a3991dec2ef44b9b7185338717a6 (diff) | |
ARM: dts: sun5i: Reorder pinctrl nodes
We try to keep the PIO nodes ordered alphabetically, but this doesn't
always work out. Let's fix it.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/sun5i.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun5i.dtsi | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 0d71b01967a3..2fb438c4fe9d 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -504,18 +504,18 @@ bias-pull-up; }; - mmc2_8bit_pins: mmc2-8bit-pins { + mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", - "PC14", "PC15"; + "PC10", "PC11"; function = "mmc2"; drive-strength = <30>; bias-pull-up; }; - mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { + mmc2_8bit_pins: mmc2-8bit-pins { pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11"; + "PC10", "PC11", "PC12", "PC13", + "PC14", "PC15"; function = "mmc2"; drive-strength = <30>; bias-pull-up; @@ -539,6 +539,11 @@ function = "nand0"; }; + pwm0_pin: pwm0-pin { + pins = "PB2"; + function = "pwm"; + }; + spi2_pe_pins: spi2-pe-pins { pins = "PE1", "PE2", "PE3"; function = "spi2"; @@ -578,11 +583,6 @@ pins = "PG11", "PG12"; function = "uart3"; }; - - pwm0_pin: pwm0-pin { - pins = "PB2"; - function = "pwm"; - }; }; timer@1c20c00 { |