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authorPatrick Menschel <menschel.p@posteo.de>2017-04-03 19:00:14 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-04-04 17:42:22 +0200
commit86daa3d30b3e90a172f241d5253b5296b98b17b9 (patch)
tree41823d8d920aadbf985942c500dfae5798dd17ce /arch/arm/boot/dts/sun7i-a20.dtsi
parentd2a20efbb11ba97fbca05d7ec7ffcec3493f6ded (diff)
ARM: dts: sun7i: Add can0_pins_a pinctrl settings
The A20 SoC has an on-board CAN controller. This patch adds the pinctrl settings for pins PH20 and PH21. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi')
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index ff742a5f046d..87491639ecfd 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1095,6 +1095,11 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ can0_pins_a: can0@0 {
+ pins = "PH20", "PH21";
+ function = "can";
+ };
+
clk_out_a_pins_a: clk_out_a@0 {
pins = "PI12";
function = "clk_out_a";