diff options
author | Chen-Yu Tsai <wens@csie.org> | 2018-09-26 21:23:39 +0800 |
---|---|---|
committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-09-29 15:58:38 +0200 |
commit | 6eeb4180d4b9887b6bc8bbe0a22c1ce3634417f0 (patch) | |
tree | 0e4bd29b2bb1a1ae867e6e8428ac5b51a84efe86 /arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | |
parent | 36c4bef372a114222266858b1f342f7c03fabdd7 (diff) |
ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees
Bananapi released an updated revision of the H3/H5 based Bananapi M2+.
Version 1.2 enables voltage control for the CPU's regulator by using
a GPIO line to toggle a MOSFET that can change the effective resistance
value in the regulator's feedback network.
This patch adds a common .dtsi file for this new revision, which
includes the original common sunxi-bananapi-m2-plus.dtsi file, and
adds the GPIO-controlled regulator and a cpu-supply reference. H3
and H5 variant dts files are added as well.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi')
-rw-r--r-- | arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi new file mode 100644 index 000000000000..53edd1faee99 --- /dev/null +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org> + */ + +#include "sunxi-bananapi-m2-plus.dtsi" + +/ { + /* + * Bananapi M2+ v1.2 uses a GPIO line to change the effective + * resistance on the CPU regulator's feedback pin. + */ + reg_vdd_cpux: vdd-cpux { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ + gpios-states = <0x1>; + states = <1100000 0x0 + 1300000 0x1>; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; |