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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2018-09-02 12:08:54 +0200
committerThierry Reding <treding@nvidia.com>2018-09-26 16:55:16 +0200
commit351c72c8323589351090504515d081384c3ea705 (patch)
treea291206d0e5fbf752ba2bbf5d75b71b8d3063184 /arch/arm/boot/dts/tegra20-colibri.dtsi
parent0b51e73ba1e9d4ae6564449e7434f958839779f7 (diff)
ARM: tegra: colibri_t20: add gpio hogs for gmi_wr_n buffers
Add GPIO hogs for GMI_WR_N buffers: - tri-stating GMI_WR_N on SODIMM pin 99 nPWE - not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-colibri.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra20-colibri.dtsi16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi
index 281e0dd11565..aba56b447bcd 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -757,4 +757,20 @@
output-high;
line-name = "LAN_RESET#";
};
+
+ /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
+ npwe {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "Tri-state nPWE";
+ };
+
+ /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
+ rdnwr {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "Not tri-state RDnWR";
+ };
};