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| author | Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> | 2021-01-11 12:07:54 +0000 |
|---|---|---|
| committer | Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> | 2021-01-11 12:07:54 +0000 |
| commit | 3d99c47ffcad87e2d59b8ef6615d36b5d67dd76b (patch) | |
| tree | 33bc36fe6a7cd18e0e7100b00e9bd87fbd1433a4 /arch/arm/include | |
| parent | 25100dfc5e6c59f35ca8d3f777c89dec040115b9 (diff) | |
| parent | 42af416d71462a72b02ba6ac632c8dcb9ce729a0 (diff) | |
Merge tag 'v5.4.81' into 5.4-2.3.x-imx
This is the 5.4.81 stable release
Conflicts (manual resolve):
- drivers/tee/optee/call.c:
Drop commit e0238fcd9f3a0 ("MLK-21698: tee:optee: fix shared memory
page attribute checks") from NXP in favor of 0e467f6af99f ("optee:
add writeback to valid memory type") from upstream as including the
WT-marked memory blocks is not compatible with OP-TEE design.
Link:
https://lore.kernel.org/lkml/AM6PR06MB4691D4988AC57DD24424D40CA6F30@AM6PR06MB4691.eurprd06.prod.outlook.com/
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/pgtable-2level.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/pgtable-3level.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 51beec41d48c..50b51ac91fcb 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -75,6 +75,8 @@ #define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) +#define MAX_POSSIBLE_PHYSMEM_BITS 32 + /* * PMD_SHIFT determines the size of the area a second-level page table can map * PGDIR_SHIFT determines what a third-level page table entry can map diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 5b18295021a0..8006a56cc2ce 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -25,6 +25,8 @@ #define PTE_HWTABLE_OFF (0) #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64)) +#define MAX_POSSIBLE_PHYSMEM_BITS 40 + /* * PGDIR_SHIFT determines the size a top-level page table entry can map. */ |