diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2020-09-21 08:57:44 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2020-09-22 14:54:08 +0800 |
| commit | 41fae930efd1b0c4e78c7e3419b81dacee39097e (patch) | |
| tree | ad932c0e17d680cf5db8a6f37f6a518296d916b7 /arch/arm/mach-imx | |
| parent | 5a50ac86e8816ddf86fd18a938e425dfa4511b3e (diff) | |
MLK-24821 ARM: imx: Increase RBC counter to for successful LPM mode enter on i.MX7D
Current RBC counter value of 0x8(~240us) is NOT enough to block interrupt
when entering low power mode, when interrupt arrives during the window of
GIC dist disabled and low power mode enter NOT finished, system will stuck
at WFI and never wake up, increasing RBC counter can avoid this situation,
since the latency introduced by RBC counter is quite trivial, so here just
use the MAX value of 0x3f(~2ms) to make it safe enough.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/cpuidle-imx7d.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx7d_low_power_idle.S | 7 | ||||
| -rw-r--r-- | arch/arm/mach-imx/suspend-imx7.S | 7 |
3 files changed, 8 insertions, 10 deletions
diff --git a/arch/arm/mach-imx/cpuidle-imx7d.c b/arch/arm/mach-imx/cpuidle-imx7d.c index 8e1e61c5503b..e38c2c78290b 100644 --- a/arch/arm/mach-imx/cpuidle-imx7d.c +++ b/arch/arm/mach-imx/cpuidle-imx7d.c @@ -258,8 +258,8 @@ static struct cpuidle_driver imx7d_cpuidle_driver = { }, /* LOW POWER IDLE */ { - .exit_latency = 10000, - .target_residency = 20000, + .exit_latency = 12000, + .target_residency = 22000, .flags = CPUIDLE_FLAG_TIMER_STOP, .enter = imx7d_enter_low_power_idle, .name = "LOW-POWER-IDLE", diff --git a/arch/arm/mach-imx/imx7d_low_power_idle.S b/arch/arm/mach-imx/imx7d_low_power_idle.S index 85c229700ec4..cad438ec7f97 100644 --- a/arch/arm/mach-imx/imx7d_low_power_idle.S +++ b/arch/arm/mach-imx/imx7d_low_power_idle.S @@ -641,13 +641,12 @@ ENTRY(imx7d_low_power_idle) /* * enable the RBC bypass counter here * to hold off the interrupts. RBC counter - * = 8 (240us). With this setting, the latency + * = 8 (2ms). With this setting, the latency * from wakeup interrupt to ARM power up - * is ~250uS. + * is ~2ms. */ ldr r8, [r10, #0x14] - bic r8, r8, #(0x3f << 24) - orr r8, r8, #(0x8 << 24) + orr r8, r8, #(0x3f << 24) str r8, [r10, #0x14] /* enable the counter. */ diff --git a/arch/arm/mach-imx/suspend-imx7.S b/arch/arm/mach-imx/suspend-imx7.S index 5f4e31152a69..1fb9333ad5b4 100644 --- a/arch/arm/mach-imx/suspend-imx7.S +++ b/arch/arm/mach-imx/suspend-imx7.S @@ -602,13 +602,12 @@ ddr_retention_enter_out: /* * enable the RBC bypass counter here * to hold off the interrupts. RBC counter - * = 8 (240us). With this setting, the latency + * = 0x3f (2ms). With this setting, the latency * from wakeup interrupt to ARM power up - * is ~250uS. + * is ~2ms. */ ldr r8, [r11, #0x14] - bic r8, r8, #(0x3f << 24) - orr r8, r8, #(0x8 << 24) + orr r8, r8, #(0x3f << 24) str r8, [r11, #0x14] /* enable the counter. */ |