diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2019-03-01 10:35:32 +0200 |
|---|---|---|
| committer | Robert Chiras <robert.chiras@nxp.com> | 2019-03-05 10:37:08 +0200 |
| commit | 1711a0a5e25d995ea538830b85b45b25b1d0a2ce (patch) | |
| tree | d7748e3e2468962d11436763732dffe8ec72776f /arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | |
| parent | bd6e78b9ca9cf587119bd8659f6153a4966d0324 (diff) | |
MLK-20718-3: arm64: dts: imx8dx: Use DSI PHY_REF clk
Until now, the DSI PHY_REF clock was by default ON in SCFW, which made
this clock unusable in kernel, therefore, this clock was set as
CLK_DUMMY in DSI device nodes.
Sinnce this clock was set to OFF in SCFW, now it can be used from
kernel, so add it to device nodes so that the driver can use it
properly.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index cdc546fd4a52..3dd2429f1fd5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -1834,18 +1834,20 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&irqsteer_mipi_lvds0>; clocks = - <&clk IMX8QXP_MIPI0_BYPASS_CLK>, + <&clk IMX8QXP_MIPI0_DSI_PHY_CLK>, <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; clock-names = "phy_ref", "tx_esc", "rx_esc"; assigned-clocks = + <&clk IMX8QXP_MIPI0_DSI_PHY_SEL>, <&clk IMX8QXP_MIPI0_DSI_TX_ESC_SEL>, <&clk IMX8QXP_MIPI0_DSI_RX_ESC_SEL>, <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; - assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; + assigned-clock-rates = <0>, <0>, <0>, <18000000>, <72000000>; assigned-clock-parents = <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>, + <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>, <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>; power-domains = <&pd_mipi_dsi0>; phys = <&mipi_dsi_phy1>; @@ -1864,7 +1866,7 @@ clocks = <&clk IMX8QXP_MIPI0_PIXEL_CLK>, <&clk IMX8QXP_MIPI0_BYPASS_CLK>, - <&clk IMX8QXP_CLK_DUMMY>; + <&clk IMX8QXP_MIPI0_DSI_PHY_CLK>; clock-names = "pixel", "bypass", "phy_ref"; power-domains = <&pd_mipi_dsi0>; csr = <&mipi_dsi_csr1>; @@ -2010,18 +2012,20 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&irqsteer_mipi_lvds1>; clocks = - <&clk IMX8QXP_MIPI1_BYPASS_CLK>, + <&clk IMX8QXP_MIPI1_DSI_PHY_CLK>, <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>, <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>; clock-names = "phy_ref", "tx_esc", "rx_esc"; assigned-clocks = + <&clk IMX8QXP_MIPI1_DSI_PHY_SEL>, <&clk IMX8QXP_MIPI1_DSI_TX_ESC_SEL>, <&clk IMX8QXP_MIPI1_DSI_RX_ESC_SEL>, <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>, <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>; - assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; + assigned-clock-rates = <0>, <0>, <0>, <18000000>, <72000000>; assigned-clock-parents = <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>, + <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>, <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>; power-domains = <&pd_mipi_dsi1>; phys = <&mipi_dsi_phy2>; @@ -2040,7 +2044,7 @@ clocks = <&clk IMX8QXP_MIPI1_PIXEL_CLK>, <&clk IMX8QXP_MIPI1_BYPASS_CLK>, - <&clk IMX8QXP_CLK_DUMMY>; + <&clk IMX8QXP_MIPI1_DSI_PHY_CLK>; clock-names = "pixel", "bypass", "phy_ref"; power-domains = <&pd_mipi_dsi1>; csr = <&mipi_dsi_csr2>; |