diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2018-07-27 15:53:06 +0300 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:34:36 +0800 |
| commit | 754277b7c33b31ce87a77eaa3b0d952682ed3805 (patch) | |
| tree | 3c31301249881652f903240cb75f501094ffe6f1 /arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | |
| parent | 59b95e0043cc4d8a18ce17b6a1950f9dca8638f3 (diff) | |
MLK-18789-5: ARM64: dts: imx8dx: Add dts file for lcdif
Add nodes for the ADMA eLCDIF controller found in i.MX8QXP and specific
dts file for it's usage with the Seiko 43WVF1G LCD panel.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 54 |
1 files changed, 40 insertions, 14 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index 4c99c9deadd7..3f2ba6670d01 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -821,6 +821,20 @@ #address-cells = <1>; #size-cells = <0>; + pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL { + reg = <SC_R_ELCDIF_PLL>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lcd0: PD_DMA_LCD_0 { + reg = <SC_R_LCD_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma_elcdif_pll>; + }; + }; + pd_dma_flexcan0: PD_DMA_CAN_0 { reg = <SC_R_CAN_0>; #power-domain-cells = <0>; @@ -982,20 +996,6 @@ #power-domain-cells = <0>; power-domains = <&pd_dma>; }; - - pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL { - reg = <SC_R_ELCDIF_PLL>; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - #address-cells = <1>; - #size-cells = <0>; - - pd_dma_lcd0: PD_DMA_LCD_0 { - reg = <SC_R_LCD_0>; - #power-domain-cells = <0>; - power-domains = <&pd_dma_elcdif_pll>; - }; - }; }; pd_gpu: gpu-power-domain { @@ -1747,6 +1747,32 @@ power-domains = <&pd_mipi_dsi0>; }; + adma_lcdif: lcdif@5a180000 { + compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; + reg = <0x0 0x5a180000 0x0 0x10000>; + clocks = <&clk IMX8QXP_LCD_CLK>, <&clk IMX8QXP_LCD_IPG_CLK>; + clock-names = "pix", "disp_axi"; + assigned-clocks = <&clk IMX8QXP_LCD_SEL>, <&clk IMX8QXP_ELCDIF_PLL>; + assigned-clock-rates = <804000000>, <804000000>; + assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_dma_lcd0>; + status = "disabled"; + }; + + pwm_adma_lcdif: pwm@5a190000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5a190000 0 0x1000>; + clocks = <&clk IMX8QXP_PWM_IPG_CLK>, + <&clk IMX8QXP_PWM_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_PWM_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_dma_pwm0>; + status = "disabled"; + }; + mipi_dsi_csr1: csr@56221000 { compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon"; reg = <0x0 0x56221000 0x0 0x1000>; |