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authorStoica Cosmin-Stefan <cosmin.stoica@nxp.com>2019-02-25 14:24:45 +0200
committerClark Wang <xiaoning.wang@nxp.com>2019-02-28 18:20:23 +0800
commit931a2276a3a972f98b8f79ced2f1afc313d519c6 (patch)
tree89dcf9ec30dd3581f2eca1ce8eeb118e077152b3 /arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
parent24114dc65f7886a4acf428db82996b3229962abd (diff)
MLK-20984: arm64: dts: Add IPG clock for i2c0 and i2c2
The IPG clock is introduced for i2c0 and i2c2 nodes in order to do properly clock gating/ungating for i2c0 and i2c2. 'ipg' clock drives the access to the device iomapped registers, so with this patch we are now able to read I2C registers. Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
index 43c1777de013..cdc546fd4a52 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
@@ -2378,8 +2378,9 @@
reg = <0x0 0x5a800000 0x0 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&clk IMX8QXP_I2C0_CLK>;
- clock-names = "per";
+ clocks = <&clk IMX8QXP_I2C0_CLK>,
+ <&clk IMX8QXP_I2C0_IPG_CLK>;
+ clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c0>;
@@ -2405,8 +2406,9 @@
reg = <0x0 0x5a820000 0x0 0x4000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&clk IMX8QXP_I2C2_CLK>;
- clock-names = "per";
+ clocks = <&clk IMX8QXP_I2C2_CLK>,
+ <&clk IMX8QXP_I2C2_IPG_CLK>;
+ clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c2>;