diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2018-05-17 16:46:45 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:52 +0800 |
| commit | 11100c75a85c2202ec49f4a052712bb6e4e27de3 (patch) | |
| tree | a19b8dcb47623902cae2197bd174ea3b325c0312 /arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi | |
| parent | 7ee96d85c05b8780b3256aa33a25ab0f9ccba2c3 (diff) | |
MLK-18298-1 ARM64: dts: imx8mm: enable pcie
Add the pcie support for imx8mm and verify
it on imx8mm evk board when internal pll is
used as ref clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi index 5da6b3dd8983..f483f0a9e0b0 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi @@ -883,6 +883,36 @@ }; }; + pcie0: pcie@0x33800000 { + compatible = "fsl,imx8mm-pcie", "snps,dw-pcie"; + reg = <0x0 0x33800000 0x0 0x400000>, <0x0 0x32f00000 0x0 0x10000>, + <0x0 0x1ff00000 0x0 0x80000>; + reg-names = "dbi", "phy", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_CTRL_CG>, + <&clk IMX8MM_CLK_PCIE1_PHY_CG>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + ctrl-id = <0>; + power-domains = <&pcie0_pd>; + status = "disabled"; + }; + vpu_h1: vpu_h1@38320000 { compatible = "nxp,imx8mm-hantro-h1"; reg = <0x0 0x38320000 0x0 0x10000>; |