diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-07-16 14:43:28 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:32:44 +0800 |
| commit | a1247a1af9a77434393f35822be3f87699d64587 (patch) | |
| tree | ce3b3777db820564b2d145ae1ba55f02ce310a47 /arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi | |
| parent | 6c5e993ac91868ea050ae6c963051dcb8d87047a (diff) | |
MLK-18427-02 ARM64: dts: freescale: add busfreq mode for imx8mm
Add busfreq node support on i.MX8MM. busfreq support is enabled by
default, but it need to be disabled on DDR4 validation board at present.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 6d5307eb88a6f5bfdb7123fd9165681cd5a31c7d)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi index a3a3184bccdf..b0162f68eb03 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi @@ -110,6 +110,24 @@ interrupt-parent = <&gic>; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MM_DRAM_PLL_OUT>, <&clk IMX8MM_CLK_DRAM_ALT_SRC>, + <&clk IMX8MM_CLK_DRAM_APB_SRC>, <&clk IMX8MM_CLK_DRAM_APB_PRE_DIV>, + <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>, + <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC_DIV>, + <&clk IMX8MM_CLK_AHB_DIV>, <&clk IMX8MM_CLK_MAIN_AXI_SRC>, + <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m"; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + }; + ddr_pmu0: ddr_pmu@3d800000 { compatible = "fsl,imx8m-ddr-pmu", "fsl,imx8-ddr-pmu"; reg = <0x0 0x3d800000 0x0 0x400000>; |