diff options
| author | Chenyan Feng <ella.feng@nxp.com> | 2018-07-12 01:15:03 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:32:29 +0800 |
| commit | d9eafd067136c7a42469b28f00ff6b93270d7f00 (patch) | |
| tree | 36b8394a38f985e83a24e816c3b574beece6c36c /arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi | |
| parent | e4db12017599c1817bf22e5a3ab428c2d236533a (diff) | |
MGS-4073 [#ccc] Set GPU AHB CLK to 400M
Set GPU AHB CLK to 400M to meet design requirement.
Date: 11th Jul, 2018
Signed-off-by: Ella Feng <ella.feng@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi index a395b70488ac..f925e040d8d9 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi @@ -1091,9 +1091,9 @@ "gpu2d_clk", "gpu2d_axi_clk", "gpu2d_ahb_clk"; - assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, <&clk IMX8MM_CLK_GPU2D_SRC>, <&clk IMX8MM_CLK_GPU_AXI_SRC>, <&clk IMX8MM_CLK_GPU_AHB_SRC>,<&clk IMX8MM_GPU_PLL_OUT>; + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, <&clk IMX8MM_CLK_GPU2D_SRC>, <&clk IMX8MM_CLK_GPU_AXI_SRC>, <&clk IMX8MM_CLK_GPU_AHB_SRC>,<&clk IMX8MM_GPU_PLL_OUT>, <&clk IMX8MM_CLK_GPU_AHB_DIV>; assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>,<&clk IMX8MM_GPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <0>, <0>, <0>,<0>,<1000000000>; + assigned-clock-rates = <0>, <0>, <0>,<0>,<1000000000>, <400000000>; power-domains = <&gpu_mix_pd>; |