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authorFancy Fang <chen.fang@nxp.com>2018-07-18 18:38:26 +0800
committerJason Liu <jason.hui.liu@nxp.com>2019-02-12 10:33:01 +0800
commitde72f10744258b4819c2f2cbcd431493a00a3f57 (patch)
treea2ee3db5f5eea259595ec264b333a4c5d33da493 /arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi
parent6a427c8e9c4ae06cb84a7d8c70b7a95cf92b4206 (diff)
MLK-19017-1 ARM64: dts: imx8mm: re-order display nodes
The devices in the device tree are registered in the top-down order. But when system suspend entered, the device tree is walked in a bottom-up order to suspend devices. So change the display device nodes register order to be: LCDIF -> SEC DSIM -> Display Subsystem Since in display subystem, it will disable the whole display pipeline. So this should be first suspended before LCDIF and SEC DSIM. And besides, the SEC DSIM is better to be suspended before LCDIF which is the same with the sequence for display pipeline disables. And when system resume entered, the devices resume sequence is: LCDIF -> SEC DSIM -> Display Subsystem Which is a top-down order and is the correct sequence for display devices resume. Signed-off-by: Fancy Fang <chen.fang@nxp.com> (cherry picked from commit 4ce74783e6a50898a433372f5968175b20d4ef0c)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi')
-rwxr-xr-xarch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi
index 4fb1b97cf3b0..eec49a62ae2f 100755
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi
@@ -1003,11 +1003,6 @@
};
};
- display-subsystem {
- compatible = "fsl,imx-display-subsystem";
- ports = <&lcdif_disp0>;
- };
-
mipi_dsi: mipi_dsi@32E10000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -1033,6 +1028,11 @@
};
};
+ display-subsystem {
+ compatible = "fsl,imx-display-subsystem";
+ ports = <&lcdif_disp0>;
+ };
+
pcie0: pcie@0x33800000 {
compatible = "fsl,imx8mm-pcie", "snps,dw-pcie";
reg = <0x0 0x33800000 0x0 0x400000>, <0x0 0x32f00000 0x0 0x10000>,