diff options
| author | Han Xu <han.xu@nxp.com> | 2019-02-22 10:44:56 -0600 |
|---|---|---|
| committer | Han Xu <han.xu@nxp.com> | 2019-02-22 11:33:53 -0600 |
| commit | d41755047439c3de199c95ce9f408af0e9d0bb31 (patch) | |
| tree | d772cf68a356aeca73581dba9ef4119766f7c4f3 /arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts | |
| parent | 87016bd6f17bd3a53232c1a20b6ad0c4f3fa7f31 (diff) | |
MLK-20374: arm64: dts: change fspi PAD drive strength to avoid overshoot
change the flexspi pad settings to pull_up and drive_low to avoid
overshoot.
Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit f55654688059a337490915cd6f652d0585597f3d)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts index 96e18e98265f..5a8487e26923 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts @@ -478,22 +478,22 @@ pinctrl_flexspi0: flexspi0grp { fsl,pins = < - SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c - SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c - SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c - SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c - SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c - SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c - SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c - SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c - SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c - SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c - SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c - SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c - SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c - SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c - SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c - SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 >; }; |