diff options
| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2018-01-31 10:57:35 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:30:28 +0800 |
| commit | 7a7bea583a1f2e28b22d1f7a7ebb090f48078128 (patch) | |
| tree | bbdf1919a819c6ab9db9d870d53f496f10a349cc /arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts | |
| parent | 2fb731cb7829763849f998c23e3210bbccd665f3 (diff) | |
MLK-17455: ARM64: dts: correct the pinctrl setting for audio peripheral
According to the Reference manual, the bit 1-4 of PAD setting is reserved.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts index fb2fa75d5de6..272259c24442 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts @@ -218,16 +218,16 @@ pinctrl_esai0: esai0grp { fsl,pins = < - SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc600004c - SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc600004c - SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc600004c - SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc600004c - SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc600004c - SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc600004c - SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc600004c - SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc600004c - SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc600004c - SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc600004c + SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 >; }; @@ -330,11 +330,11 @@ pinctrl_sai1: sai1grp { fsl,pins = < - SC_P_SAI1_RXD_AUD_SAI1_RXD 0x0600004c - SC_P_SAI1_RXC_AUD_SAI1_RXC 0x0600004c - SC_P_SAI1_RXFS_AUD_SAI1_RXFS 0x0600004c - SC_P_SAI1_TXD_AUD_SAI1_TXD 0x0600006c - SC_P_SAI1_TXC_AUD_SAI1_TXC 0x0600004c + SC_P_SAI1_RXD_AUD_SAI1_RXD 0x06000040 + SC_P_SAI1_RXC_AUD_SAI1_RXC 0x06000040 + SC_P_SAI1_RXFS_AUD_SAI1_RXFS 0x06000040 + SC_P_SAI1_TXD_AUD_SAI1_TXD 0x06000060 + SC_P_SAI1_TXC_AUD_SAI1_TXC 0x06000040 >; }; |