MLK-20693-4: ARM64: dts: Move clocks of peripheral to dsp devices

Move clocks of peripheral to dsp devices, and refine the power tree

We need to control them in one driver,  if in separate driver
For example, fsl_dsp_cpu enter suspend, the clock is closed
then turn to fsl_dsp, which need to send the suspend command to dsp
but the dsp framework can’t access the device(ESAI), then the
system will hang

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>

1 files changed, 57 insertions, 19 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsp.dts
index d975b50840b7..70c0fbdd8171 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsp.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsp.dts
@@ -16,25 +16,6 @@
 		compatible = "fsl,dsp-audio";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_esai0>;
-		clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>,
-			<&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>,
-			<&clk IMX8QXP_AUD_ASRC_0_IPG>,
-			<&clk IMX8QXP_CLK_DUMMY>,
-			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
-			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
-			<&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
-			<&clk IMX8QXP_ACM_AUD_CLK1_SEL>;
-
-		clock-names = "bus", "mclk", "ipg", "mem",
-				"asrck_0", "asrck_1", "asrck_2", "asrck_3";
-		assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>,
-			<&clk IMX8QXP_AUD_PLL0_DIV>,
-			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
-			<&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
-			<&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>;
-		assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>;
-		assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
-		power-domains = <&pd_esai0>;
 		status = "okay";
 	};
 
@@ -76,7 +57,33 @@
 	status = "okay";
 };
 
+&dsp {
+	compatible = "fsl,imx8qxp-dsp";
+	reserved-region = <&dsp_reserved>;
+	reg = <0x0 0x596e8000 0x0 0x88000>;
+	clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>,
+		<&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>,
+		<&clk IMX8QXP_AUD_ASRC_0_IPG>,
+		<&clk IMX8QXP_CLK_DUMMY>,
+		<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
+		<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
+		<&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
+		<&clk IMX8QXP_ACM_AUD_CLK1_SEL>;
+	clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem",
+			"asrck_0", "asrck_1", "asrck_2", "asrck_3";
+	assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>,
+		<&clk IMX8QXP_AUD_PLL0_DIV>,
+		<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
+		<&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
+		<&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>;
+	assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>;
+	assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
+	fsl,dsp-firmware = "imx/dsp/hifi4.bin";
+	power-domains = <&pd_dsp>;
+};
+
 /delete-node/ &pd_dma0_chan6;
+/delete-node/ &pd_dsp_mu_A;
 
 &pd_asrc0 {
 	reg = <SC_R_ASRC_0>;
@@ -103,6 +110,37 @@
 				reg = <SC_R_ESAI_0>;
 				#power-domain-cells = <0>;
 				power-domains =<&pd_dma0_chan7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dsp_mu_A: PD_DSP_MU_A {
+					reg = <SC_R_MU_13A>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_esai0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dsp_mu_B: PD_DSP_MU_B {
+						reg = <SC_R_MU_13B>;
+						#power-domain-cells = <0>;
+						power-domains =<&pd_dsp_mu_A>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						pd_dsp_ram: PD_AUD_OCRAM {
+							reg = <SC_R_DSP_RAM>;
+							#power-domain-cells = <0>;
+							power-domains =<&pd_dsp_mu_B>;
+							#address-cells = <1>;
+							#size-cells = <0>;
+							pd_dsp: PD_AUD_DSP {
+								reg = <SC_R_DSP>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_dsp_ram>;
+							};
+						};
+					};
+				};
 			};
 		};
 	};