ARM64: dts: imx8qxp: enable audio modules

enable audio modules

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>

1 files changed, 341 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 62921ddbf9fe..4072d86c58cd 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -308,4 +308,345 @@ adma_subsys: bus@59000000 {
 		fsl,clk-source = <0>;
 		status = "disabled";
 	};
+
+	adma_acm: acm@59e00000 {
+		compatible = "nxp,imx8qxp-acm";
+		reg = <0x59e00000 0x1D0000>;
+		#clock-cells = <1>;
+		power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_MCLK_OUT_0>,
+				<&pd IMX_SC_R_MCLK_OUT_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>,
+				<&pd IMX_SC_R_ASRC_0>,
+				<&pd IMX_SC_R_ASRC_1>,
+				<&pd IMX_SC_R_ESAI_0>,
+				<&pd IMX_SC_R_SAI_0>,
+				<&pd IMX_SC_R_SAI_1>,
+				<&pd IMX_SC_R_SAI_2>,
+				<&pd IMX_SC_R_SAI_3>,
+				<&pd IMX_SC_R_SAI_4>,
+				<&pd IMX_SC_R_SAI_5>,
+				<&pd IMX_SC_R_SPDIF_0>,
+				<&pd IMX_SC_R_MQS_0>;
+	};
+
+	adma_dsp: dsp@596e8000 {
+		compatible = "fsl,imx8qxp-dsp";
+		reg = <0x596e8000 0x88000>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
+			 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
+			 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
+		clock-names = "ipg", "ocram", "core";
+		fsl,dsp-firmware = "imx/dsp/hifi4.bin";
+		fsl,dsp-wrap = "imx/dsp/lib_dsp_codec_wrap.so";
+		fsl,dsp-codec-mp3 = "imx/dsp/lib_dsp_mp3_dec.so";
+		fsl,dsp-codec-aac = "imx/dsp/lib_dsp_aac_dec.so";
+		power-domains = <&pd IMX_SC_R_DSP>, <&pd IMX_SC_R_DSP_RAM>;
+		power-domain-names = "dsp", "dsp_ram";
+		memory-region = <&dsp_reserved>;
+		status = "disabled";
+	};
+
+	adma_asrc0: asrc@59000000 {
+		compatible = "fsl,imx8qm-asrc0";
+		reg = <0x59000000 0x10000>;
+		interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_ASRC_0_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK>,
+			<&adma_acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+			<&adma_acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "ipg", "mem",
+			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
+			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
+			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
+			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
+			"spba";
+		dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>,
+			<&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>;
+		dma-names = "rxa", "rxb", "rxc",
+				"txa", "txb", "txc";
+		fsl,asrc-rate  = <8000>;
+		fsl,asrc-width = <16>;
+		power-domains = <&pd IMX_SC_R_ASRC_0>,
+				<&pd IMX_SC_R_DMA_0_CH0>,
+				<&pd IMX_SC_R_DMA_0_CH1>,
+				<&pd IMX_SC_R_DMA_0_CH2>,
+				<&pd IMX_SC_R_DMA_0_CH3>,
+				<&pd IMX_SC_R_DMA_0_CH4>,
+				<&pd IMX_SC_R_DMA_0_CH5>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+        };
+
+	adma_esai0: esai@59010000 {
+		compatible = "fsl,imx8qm-esai";
+		reg = <0x59010000 0x10000>;
+		interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_ESAI_0_IPG_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_ESAI_0_EXTAL_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_ESAI_0_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "core", "extal", "fsys", "spba";
+		dmas = <&edma0 6 0 1>, <&edma0 7 0 0>;
+		dma-names = "rx", "tx";
+		power-domains = <&pd IMX_SC_R_ESAI_0>,
+				<&pd IMX_SC_R_DMA_0_CH6>,
+				<&pd IMX_SC_R_DMA_0_CH7>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_spdif0: spdif@59020000 {
+		compatible = "fsl,imx8qm-spdif";
+		reg = <0x59020000 0x10000>;
+		interrupts =  <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+			<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SPDIF_0_GCLKW>, /* core */
+			<&clk IMX_CLK_DUMMY>, /* rxtx0 */
+			<&adma_lpcg IMX_ADMA_LPCG_SPDIF_0_TX_CLK>, /* rxtx1 */
+			<&clk IMX_CLK_DUMMY>, /* rxtx2 */
+			<&clk IMX_CLK_DUMMY>, /* rxtx3 */
+			<&clk IMX_CLK_DUMMY>, /* rxtx4 */
+			<&clk IMX_ADMA_IPG_CLK_ROOT>, /* rxtx5 */
+			<&clk IMX_CLK_DUMMY>, /* rxtx6 */
+			<&clk IMX_CLK_DUMMY>, /* rxtx7 */
+			<&clk IMX_CLK_DUMMY>; /* spba */
+		clock-names = "core", "rxtx0",
+				"rxtx1", "rxtx2",
+				"rxtx3", "rxtx4",
+				"rxtx5", "rxtx6",
+				"rxtx7", "spba";
+		dmas = <&edma0 8 0 5>, <&edma0 9 0 4>;
+		dma-names = "rx", "tx";
+		power-domains = <&pd IMX_SC_R_SPDIF_0>,
+				<&pd IMX_SC_R_DMA_0_CH8>,
+				<&pd IMX_SC_R_DMA_0_CH9>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai0: sai@59040000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59040000 0x10000>;
+		interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_0_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_0_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
+		power-domains = <&pd IMX_SC_R_SAI_0>,
+				<&pd IMX_SC_R_DMA_0_CH12>,
+				<&pd IMX_SC_R_DMA_0_CH13>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai1: sai@59050000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59050000 0x10000>;
+		interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_1_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_1_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
+		power-domains = <&pd IMX_SC_R_SAI_1>,
+				<&pd IMX_SC_R_DMA_0_CH14>,
+				<&pd IMX_SC_R_DMA_0_CH15>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai2: sai@59060000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59060000 0x10000>;
+		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_2_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_2_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx";
+		dmas = <&edma0 16 0 1>;
+		power-domains = <&pd IMX_SC_R_SAI_2>,
+				<&pd IMX_SC_R_DMA_0_CH16>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai3: sai@59070000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59070000 0x10000>;
+		interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_3_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_3_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx";
+		dmas = <&edma0 17 0 1>;
+		power-domains = <&pd IMX_SC_R_SAI_3>,
+				<&pd IMX_SC_R_DMA_0_CH17>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_asrc1: asrc@59800000 {
+		compatible = "fsl,imx8qm-asrc1";
+		reg = <0x59800000 0x10000>;
+		interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_ASRC_0_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK>,
+			<&adma_acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+			<&adma_acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "ipg", "mem",
+			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
+			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
+			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
+			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
+			"spba";
+		dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>,
+			<&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>;
+		dma-names = "rxa", "rxb", "rxc",
+				"txa", "txb", "txc";
+		fsl,asrc-rate  = <8000>;
+		fsl,asrc-width = <16>;
+		power-domains = <&pd IMX_SC_R_ASRC_1>,
+				<&pd IMX_SC_R_DMA_1_CH0>,
+				<&pd IMX_SC_R_DMA_1_CH1>,
+				<&pd IMX_SC_R_DMA_1_CH2>,
+				<&pd IMX_SC_R_DMA_1_CH3>,
+				<&pd IMX_SC_R_DMA_1_CH4>,
+				<&pd IMX_SC_R_DMA_1_CH5>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai4: sai@59820000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59820000 0x10000>;
+		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_4_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_4_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
+		power-domains = <&pd IMX_SC_R_SAI_4>,
+				<&pd IMX_SC_R_DMA_1_CH8>,
+				<&pd IMX_SC_R_DMA_1_CH9>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai5: sai@59830000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59830000 0x10000>;
+		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_5_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_5_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "tx";
+		dmas = <&edma1 10 0 0>;
+		power-domains = <&pd IMX_SC_R_SAI_5>,
+				<&pd IMX_SC_R_DMA_1_CH10>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_amix: amix@59840000 {
+		compatible = "fsl,imx8qm-amix";
+		reg = <0x59840000 0x10000>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_AMIX_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd IMX_SC_R_AMIX>;
+		status = "disabled";
+	};
+
+	adma_mqs: mqs@59850000 {
+		compatible = "fsl,imx8qm-mqs";
+		reg = <0x59850000 0x10000>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_MQS_IPG_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_MQS_MCLK>;
+		clock-names = "core", "mclk";
+		power-domains = <&pd IMX_SC_R_MQS_0>;
+		status = "disabled";
+	};
 };