diff options
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2019-06-28 15:18:53 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:41 +0800 |
| commit | eed9bc60b907ade100bd457f06b85cce17361ce8 (patch) | |
| tree | cdb45e8e61c338b095c634db1ad32ed8289d84db /arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | |
| parent | 13391826e5d1a02a500a1124620ec60723f35186 (diff) | |
arm64: imx8qxp: add multi-pd support for CAN1/2
Add multi-pd support for CAN1/2 due to they share CAN0's clock.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi index 681f5c426e8e..bf10636fb2d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -280,13 +280,16 @@ adma_subsys: bus@59000000 { reg = <0x5a8e0000 0x10000>; interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - /* CAN0 clock and PD is shared among all CAN instances */ clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>, <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>; assigned-clock-rates = <40000000>; - power-domains = <&pd IMX_SC_R_CAN_1>; + /* CAN1 shares CAN0's clock, to enable CAN0's clock it has + * to be powered on, so CAN1 depends on CAN0's power domain. + */ + power-domains = <&pd IMX_SC_R_CAN_1>, <&pd IMX_SC_R_CAN_0>; + power-domain-names = "can_pd", "can_aux_pd"; /* SLSlice[4] */ fsl,clk-source = <0>; status = "disabled"; @@ -297,13 +300,16 @@ adma_subsys: bus@59000000 { reg = <0x5a8f0000 0x10000>; interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - /* CAN0 clock and PD is shared among all CAN instances */ clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>, <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>; assigned-clock-rates = <40000000>; - power-domains = <&pd IMX_SC_R_CAN_2>; + /* CAN2 shares CAN0's clock, to enable CAN0's clock it has + * to be powered on, so CAN2 depends on CAN0's power domain. + */ + power-domains = <&pd IMX_SC_R_CAN_2>, <&pd IMX_SC_R_CAN_0>; + power-domain-names = "can_pd", "can_aux_pd"; /* SLSlice[4] */ fsl,clk-source = <0>; status = "disabled"; |