diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-11-11 10:19:07 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:09:36 +0800 |
| commit | 0f48f49add1fb8fd350739c3ddc061eb213274ef (patch) | |
| tree | 0a55c7935b8d801f9170e08475645cf979979b07 /arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | |
| parent | 0e98761734b65141302c19c85c0b03ed0b8f6515 (diff) | |
arm64: imx8-ss-dc1.dtsi: Add dc1_dpr1_channel3 and dc1_dpr2_channel1-3 phandles for dpu2
This patch adds dc1_dpr1_channel3 and dc1_dpr2_channel1-3 phandles for dpu2
node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi index 42b91604fd81..23d507731725 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi @@ -467,7 +467,11 @@ dc1_subsys: bus@57000000 { <&pd IMX_SC_R_DC_1_PLL_1>; power-domain-names = "dc", "pll0", "pll1"; fsl,dpr-channels = <&dc1_dpr1_channel1>, - <&dc1_dpr1_channel2>; + <&dc1_dpr1_channel2>, + <&dc1_dpr1_channel3>, + <&dc1_dpr2_channel1>, + <&dc1_dpr2_channel2>, + <&dc1_dpr2_channel3>; status = "disabled"; }; }; |