diff options
| author | Sandor Yu <Sandor.yu@nxp.com> | 2019-08-22 14:12:48 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:06:44 +0800 |
| commit | 5a8a6c85de3a9bc3b1bf79701a3c9ccfc53dd9da (patch) | |
| tree | ce177e33e79b10f1f9baed5c386344df0b3c184b /arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | |
| parent | f40ec652a955071febb3af14be1f378778d9054f (diff) | |
arm64: imx8-ss-dc0/1.dtsi: add dc0/1_disp clocks for dpu0/1
disp0/1 lpcg clocks parent are fixed.
so dc0/1_disp0/1 clocks couldn't replace by disp0/1_lpcg clocks.
Add dc0/1 disp clocks and disp0/1_lpcg clocks for dc0/1.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi index 49da21e1356f..135c0078030b 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi @@ -332,8 +332,10 @@ dc1_subsys: bus@57000000 { clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_DC_1_VIDEO0 IMX_SC_PM_CLK_BYPASS>, - <&dc1_disp_lpcg 0>, <&dc1_disp_lpcg 1>; - clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1"; + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>, + <&dc0_disp_lpcg 0>, <&dc0_disp_lpcg 1>; + clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg"; power-domains = <&pd IMX_SC_R_DC_1>, <&pd IMX_SC_R_DC_1_PLL_0>, <&pd IMX_SC_R_DC_1_PLL_1>; |