diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-07-23 10:59:15 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:12 +0800 |
| commit | 1651d4ea402b34a50b5bb265394dd285879e5856 (patch) | |
| tree | 36feafda2e442f8a4cf6b60a6c6739009f2358fb /arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | |
| parent | fafde519da8c1a5a20543b59b53038def49355f7 (diff) | |
arm64: dts: imx8: img: csi and pi lpcgs depend on ISI power
ci and pi lpcgs depend on ISI power, otherwise, accessing LPCG
will abort.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi index 00ef3b82f36f..a07aab92b703 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi @@ -37,7 +37,7 @@ img_subsys: bus@58000000 { clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>; bit-offset = <16>; clock-output-names = "csi0_lpcg_core_clk"; - power-domains = <&pd IMX_SC_R_CSI_0>; + power-domains = <&pd IMX_SC_R_ISI_CH0>; }; csi0_esc_lpcg: clock-controller@5822301c { @@ -47,7 +47,7 @@ img_subsys: bus@58000000 { clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>; bit-offset = <16>; clock-output-names = "csi0_lpcg_esc_clk"; - power-domains = <&pd IMX_SC_R_CSI_0>; + power-domains = <&pd IMX_SC_R_ISI_CH0>; }; csi1_core_lpcg: clock-controller@58243018 { @@ -57,7 +57,7 @@ img_subsys: bus@58000000 { clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>; bit-offset = <16>; clock-output-names = "csi1_lpcg_core_clk"; - power-domains = <&pd IMX_SC_R_CSI_1>; + power-domains = <&pd IMX_SC_R_ISI_CH0>; }; csi1_esc_lpcg: clock-controller@5824301c { @@ -67,7 +67,7 @@ img_subsys: bus@58000000 { clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>; bit-offset = <16>; clock-output-names = "csi1_lpcg_esc_clk"; - power-domains = <&pd IMX_SC_R_CSI_1>; + power-domains = <&pd IMX_SC_R_ISI_CH0>; }; pi0_pxl_lpcg: clock-controller@58263018 { @@ -77,7 +77,7 @@ img_subsys: bus@58000000 { clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; bit-offset = <0>; clock-output-names = "pi0_lpcg_pxl_clk"; - power-domains = <&pd IMX_SC_R_PI_0>; + power-domains = <&pd IMX_SC_R_ISI_CH0>; }; pi0_ipg_lpcg: clock-controller@58263004 { @@ -87,7 +87,7 @@ img_subsys: bus@58000000 { clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; bit-offset = <16>; clock-output-names = "pi0_lpcg_ipg_clk"; - power-domains = <&pd IMX_SC_R_PI_0>; + power-domains = <&pd IMX_SC_R_ISI_CH0>; }; pi0_misc_lpcg: clock-controller@5826301c { @@ -97,7 +97,7 @@ img_subsys: bus@58000000 { clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>; bit-offset = <0>; clock-output-names = "pi0_lpcg_misc_clk"; - power-domains = <&pd IMX_SC_R_PI_0>; + power-domains = <&pd IMX_SC_R_ISI_CH0>; }; pdma0_lpcg: clock-controller@58500000 { |