arm64: dts: imx8: img: fully switched to new clk binding

fully switched to new clk binding

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

1 files changed, 209 insertions, 45 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
index f24075603c8c..00ef3b82f36f 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
@@ -9,31 +9,195 @@ img_subsys: bus@58000000 {
 	#size-cells = <1>;
 	ranges = <0x58000000 0x0 0x58000000 0x1000000>;
 
-	img_lpcg: clock-controller@58500000 {
-		compatible = "fsl,imx8qxp-lpcg-img";
-		reg = <0x58500000 0xb0000>;
+	img_ipg_clk: clock-img-ipg {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+		clock-output-names = "img_ipg_clk";
+	};
+
+	img_axi_clk: clock-img-axi {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <400000000>;
+		clock-output-names = "img_axi_clk";
+	};
+
+	img_pxl_clk: clock-img-pxl {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <600000000>;
+		clock-output-names = "img_pxl_clk";
+	};
+
+	csi0_core_lpcg: clock-controller@58223018 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58223018 0x4>;
 		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>;
+		bit-offset = <16>;
+		clock-output-names = "csi0_lpcg_core_clk";
+		power-domains = <&pd IMX_SC_R_CSI_0>;
 	};
 
-	csi0_lpcg: clock-controller@58223000 {
-		compatible = "fsl,imx8qxp-lpcg-csi0";
-		reg = <0x58223000 0x1000>;
+	csi0_esc_lpcg: clock-controller@5822301c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5822301c 0x4>;
 		#clock-cells = <1>;
-		status = "disabled";
+		clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>;
+		bit-offset = <16>;
+		clock-output-names = "csi0_lpcg_esc_clk";
+		power-domains = <&pd IMX_SC_R_CSI_0>;
 	};
 
-	csi1_lpcg: clock-controller@58243000 {
-		compatible = "fsl,imx8qxp-lpcg-csi1";
-		reg = <0x58243000 0x1000>;
+	csi1_core_lpcg: clock-controller@58243018 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58243018 0x4>;
 		#clock-cells = <1>;
-		status = "disabled";
+		clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>;
+		bit-offset = <16>;
+		clock-output-names = "csi1_lpcg_core_clk";
+		power-domains = <&pd IMX_SC_R_CSI_1>;
 	};
 
-	pi_lpcg: clock-controller@58263000 {
-		compatible = "fsl,imx8qxp-lpcg-pi";
-		reg = <0x58263000 0x1000>;
+	csi1_esc_lpcg: clock-controller@5824301c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5824301c 0x4>;
 		#clock-cells = <1>;
-		status = "disabled";
+		clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>;
+		bit-offset = <16>;
+		clock-output-names = "csi1_lpcg_esc_clk";
+		power-domains = <&pd IMX_SC_R_CSI_1>;
+	};
+
+	pi0_pxl_lpcg: clock-controller@58263018 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58263018 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
+		bit-offset = <0>;
+		clock-output-names = "pi0_lpcg_pxl_clk";
+		power-domains = <&pd IMX_SC_R_PI_0>;
+	};
+
+	pi0_ipg_lpcg: clock-controller@58263004 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58263004 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
+		bit-offset = <16>;
+		clock-output-names = "pi0_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_PI_0>;
+	};
+
+	pi0_misc_lpcg: clock-controller@5826301c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5826301c 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>;
+		bit-offset = <0>;
+		clock-output-names = "pi0_lpcg_misc_clk";
+		power-domains = <&pd IMX_SC_R_PI_0>;
+	};
+
+	pdma0_lpcg: clock-controller@58500000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58500000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_pxl_clk>;
+		bit-offset = <0>;
+		clock-output-names = "pdma0_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+	};
+
+	pdma1_lpcg: clock-controller@58510000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58510000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_pxl_clk>;
+		bit-offset = <0>;
+		clock-output-names = "pdma1_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH1>;
+	};
+
+	pdma2_lpcg: clock-controller@58520000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58520000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_pxl_clk>;
+		bit-offset = <0>;
+		clock-output-names = "pdma2_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH2>;
+	};
+
+	pdma3_lpcg: clock-controller@58530000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58530000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_pxl_clk>;
+		bit-offset = <0>;
+		clock-output-names = "pdma3_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH3>;
+	};
+
+	pdma4_lpcg: clock-controller@58540000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58540000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_pxl_clk>;
+		bit-offset = <0>;
+		clock-output-names = "pdma4_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH4>;
+	};
+
+	pdma5_lpcg: clock-controller@58550000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58550000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_pxl_clk>;
+		bit-offset = <0>;
+		clock-output-names = "pdma5_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH5>;
+	};
+
+	pdma6_lpcg: clock-controller@58560000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58560000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_pxl_clk>;
+		bit-offset = <0>;
+		clock-output-names = "pdma6_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH6>;
+	};
+
+	pdma7_lpcg: clock-controller@58570000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58570000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_pxl_clk>;
+		bit-offset = <0>;
+		clock-output-names = "pdma7_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH7>;
+	};
+
+	csi0_pxl_lpcg: clock-controller@58580000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58580000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_pxl_clk>;
+		bit-offset = <0>;
+		clock-output-names = "csi0_lpcg_pxl_clk";
+		power-domains = <&pd IMX_SC_R_CSI_0>;
+	};
+
+	csi1_pxl_lpcg: clock-controller@58590000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58590000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_pxl_clk>;
+		bit-offset = <0>;
+		clock-output-names = "csi1_lpcg_pxl_clk";
+		power-domains = <&pd IMX_SC_R_CSI_1>;
 	};
 
 	irqsteer_csi0: irqsteer@58220000 {
@@ -43,7 +207,7 @@ img_subsys: bus@58000000 {
 		interrupt-controller;
 		interrupt-parent = <&gic>;
 		#interrupt-cells = <1>;
-		clocks = <&clk IMX_CLK_DUMMY>;
+		clocks = <&img_ipg_clk>;
 		clock-names = "ipg";
 		fsl,channel = <0>;
 		fsl,num-irqs = <32>;
@@ -59,7 +223,7 @@ img_subsys: bus@58000000 {
 		interrupt-controller;
 		interrupt-parent = <&gic>;
 		#interrupt-cells = <1>;
-		clocks = <&clk IMX_CLK_DUMMY>;
+		clocks = <&img_ipg_clk>;
 		clock-names = "ipg";
 		fsl,channel = <0>;
 		fsl,num-irqs = <32>;
@@ -73,9 +237,9 @@ img_subsys: bus@58000000 {
 		reg = <0x58226000 0x1000>;
 		interrupts = <8>;
 		interrupt-parent = <&irqsteer_csi0>;
-		clocks = <&clk IMX_CSI0_I2C0_CLK>;
+		clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>;
 		clock-names = "per";
-		assigned-clocks = <&clk IMX_CSI0_I2C0_CLK>;
+		assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>;
 		assigned-clock-rates = <24000000>;
 		power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>;
 		status = "disabled";
@@ -86,9 +250,9 @@ img_subsys: bus@58000000 {
 		reg = <0x58246000 0x1000>;
 		interrupts = <8>;
 		interrupt-parent = <&irqsteer_csi1>;
-		clocks = <&clk IMX_CSI1_I2C0_CLK>;
+		clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>;
 		clock-names = "per";
-		assigned-clocks = <&clk IMX_CSI1_I2C0_CLK>;
+		assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>;
 		assigned-clock-rates = <24000000>;
 		power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>;
 		status = "disabled";
@@ -105,7 +269,7 @@ img_subsys: bus@58000000 {
 			reg = <0x58100000 0x10000>;
 			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
-			clocks = <&img_lpcg IMX_IMG_LPCG_PDMA0_CLK>;
+			clocks = <&pdma0_lpcg 0>;
 			clock-names = "per";
 			power-domains = <&pd IMX_SC_R_ISI_CH0>;
 			interface = <2 0 2>;
@@ -127,7 +291,7 @@ img_subsys: bus@58000000 {
 			reg = <0x58110000 0x10000>;
 			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
-			clocks = <&img_lpcg IMX_IMG_LPCG_PDMA1_CLK>;
+			clocks = <&pdma1_lpcg 0>;
 			clock-names = "per";
 			power-domains = <&pd IMX_SC_R_ISI_CH1>;
 			interface = <2 1 2>;
@@ -144,7 +308,7 @@ img_subsys: bus@58000000 {
 			reg = <0x58120000 0x10000>;
 			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
-			clocks = <&img_lpcg IMX_IMG_LPCG_PDMA2_CLK>;
+			clocks = <&pdma2_lpcg 0>;
 			clock-names = "per";
 			power-domains = <&pd IMX_SC_R_ISI_CH2>;
 			interface = <2 2 2>;
@@ -161,7 +325,7 @@ img_subsys: bus@58000000 {
 			reg = <0x58130000 0x10000>;
 			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
-			clocks = <&img_lpcg IMX_IMG_LPCG_PDMA3_CLK>;
+			clocks = <&pdma3_lpcg 0>;
 			clock-names = "per";
 			power-domains = <&pd IMX_SC_R_ISI_CH3>;
 			interface = <2 3 2>;
@@ -178,7 +342,7 @@ img_subsys: bus@58000000 {
 			reg = <0x58140000 0x10000>;
 			interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
-			clocks = <&img_lpcg IMX_IMG_LPCG_PDMA4_CLK>;
+			clocks = <&pdma4_lpcg 0>;
 			clock-names = "per";
 			power-domains = <&pd IMX_SC_R_ISI_CH4>;
 			interface = <3 0 2>;
@@ -195,7 +359,7 @@ img_subsys: bus@58000000 {
 			reg = <0x58150000 0x10000>;
 			interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
-			clocks = <&img_lpcg IMX_IMG_LPCG_PDMA5_CLK>;
+			clocks = <&pdma5_lpcg 0>;
 			clock-names = "per";
 			power-domains = <&pd IMX_SC_R_ISI_CH5>;
 			interface = <3 1 2>;
@@ -212,7 +376,7 @@ img_subsys: bus@58000000 {
 			reg = <0x58160000 0x10000>;
 			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
-			clocks = <&img_lpcg IMX_IMG_LPCG_PDMA6_CLK>;
+			clocks = <&pdma6_lpcg 0>;
 			clock-names = "per";
 			power-domains = <&pd IMX_SC_R_ISI_CH6>;
 			interface = <3 2 2>;
@@ -229,7 +393,7 @@ img_subsys: bus@58000000 {
 			reg = <0x58170000 0x10000>;
 			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
-			clocks = <&img_lpcg IMX_IMG_LPCG_PDMA7_CLK>;
+			clocks = <&pdma7_lpcg 0>;
 			clock-names = "per";
 			power-domains = <&pd IMX_SC_R_ISI_CH7>;
 			interface = <3 3 2>;
@@ -245,12 +409,12 @@ img_subsys: bus@58000000 {
 			compatible = "fsl,mxc-mipi-csi2";
 			reg = <0x58227000 0x1000>,
 			      <0x58221000 0x1000>;
-			clocks = <&csi0_lpcg IMX_CSI_LPCG_CSI0_CORE_CLK>,
-				 <&csi0_lpcg IMX_CSI_LPCG_CSI0_ESC_CLK>,
-				 <&img_lpcg IMX_IMG_LPCG_CSI0_PXL_LINK_CLK>;
+			clocks = <&csi0_core_lpcg 0>,
+				 <&csi0_esc_lpcg 0>,
+				 <&csi0_pxl_lpcg 0>;
 			clock-names = "clk_core", "clk_esc", "clk_pxl";
-			assigned-clocks = <&csi0_lpcg IMX_CSI_LPCG_CSI0_CORE_CLK>,
-					  <&csi0_lpcg IMX_CSI_LPCG_CSI0_ESC_CLK>;
+			assigned-clocks = <&csi0_core_lpcg 0>,
+					  <&csi0_esc_lpcg 0>;
 			assigned-clock-rates = <360000000>, <72000000>;
 			power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>;
 			power-domain-names = "pd_csi", "pd_isi_ch0";
@@ -261,12 +425,12 @@ img_subsys: bus@58000000 {
 			compatible = "fsl,mxc-mipi-csi2";
 			reg = <0x58247000 0x1000>,
 			      <0x58241000 0x1000>;
-			clocks = <&csi1_lpcg IMX_CSI_LPCG_CSI1_CORE_CLK>,
-				 <&csi1_lpcg IMX_CSI_LPCG_CSI1_ESC_CLK>,
-				 <&img_lpcg IMX_IMG_LPCG_CSI1_PXL_LINK_CLK>;
+			clocks = <&csi1_core_lpcg 0>,
+				 <&csi1_esc_lpcg 0>,
+				 <&csi1_pxl_lpcg 0>;
 			clock-names = "clk_core", "clk_esc", "clk_pxl";
-			assigned-clocks = <&csi1_lpcg IMX_CSI_LPCG_CSI1_CORE_CLK>,
-					  <&csi1_lpcg IMX_CSI_LPCG_CSI1_ESC_CLK>;
+			assigned-clocks = <&csi1_core_lpcg 0>,
+					  <&csi1_esc_lpcg 0>;
 			assigned-clock-rates = <360000000>, <72000000>;
 			power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>;
 			power-domain-names = "pd_csi", "pd_isi_ch0";
@@ -276,13 +440,13 @@ img_subsys: bus@58000000 {
 		parallel_csi: pcsi@58261000 {
 			compatible = "fsl,mxc-parallel-csi";
 			reg = <0x58261000 0x1000>;
-			clocks = <&pi_lpcg IMX_PI_LPCG_PI0_PIXEL_CLK>,
-				 <&pi_lpcg IMX_PI_LPCG_PI0_IPG_CLK>,
-				 <&clk IMX_PARALLEL_PER_DIV_CLK>,
-				 <&clk IMX_PARALLEL_DPLL_CLK>;
+			clocks = <&pi0_pxl_lpcg 0>,
+				 <&pi0_ipg_lpcg 0>,
+				 <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>,
+				 <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>;
 			clock-names = "pixel", "ipg", "div", "dpll";
-			assigned-clocks = <&clk IMX_PARALLEL_PER_DIV_CLK>;
-			assigned-clock-parents = <&clk IMX_PARALLEL_DPLL_CLK>;
+			assigned-clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
+			assigned-clock-parents = <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>;
 			assigned-clock-rates = <160000000>;  /* 160MHz */
 			power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>;
 			power-domain-names = "pd_pi", "pd_isi_ch0";