arm64: dts: imx8: add vpu support

add vpu support

Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>

1 files changed, 58 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
new file mode 100644
index 000000000000..f289e15f15ea
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *	Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+vpu_subsys: bus@2c000000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
+
+	vpu_lpcg: clock-controller@2d000000 {
+		compatible = "fsl,imx8qxp-lpcg-vpu";
+		reg = <0x2c000000 0x2000000>;
+		#clock-cells = <1>;
+		status = "disabled";
+	};
+
+	vpu_decoder: vpu_decoder@2c000000 {
+		compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
+		reg = <0x2c000000 0x1000000>;
+		reg-names = "vpu_regs";
+		power-domains = <&pd IMX_SC_R_VPU_DEC_0>,
+				<&pd IMX_SC_R_VPU>, <&pd IMX_SC_R_VPU_MU_0>;
+		power-domain-names = "vpudec", "vpu", "vpumu0";
+		status = "disabled";
+	};
+
+	vpu_encoder: vpu_encoder@2d000000 {
+		compatible = "nxp,imx8qxp-b0-vpuenc";
+		reg = <0x2d000000 0x1000000>,	/*VPU Encoder*/
+			<0x2c000000 0x2000000>; /*VPU*/
+		reg-names = "vpu_regs";
+		power-domains = <&pd IMX_SC_R_VPU_ENC_0>,
+				<&pd IMX_SC_R_VPU>, <&pd IMX_SC_R_VPU_MU_1>;
+		power-domain-names = "vpuenc", "vpu", "vpumu1";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		status = "disabled";
+	};
+
+	mu_m0: mu_m0@2d000000 {
+		compatible = "fsl,imx8-mu0-vpu-m0";
+		reg = <0x2d000000 0x20000>;
+		interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <16>;
+		status = "okay";
+	};
+
+	mu1_m0: mu1_m0@2d020000 {
+		compatible = "fsl,imx8-mu1-vpu-m0";
+		reg = <0x2d020000 0x20000>;
+		interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <17>;
+		status = "okay";
+	};
+};