diff options
| author | Han Xu <han.xu@nxp.com> | 2020-03-26 15:47:52 -0500 |
|---|---|---|
| committer | Han Xu <han.xu@nxp.com> | 2020-03-30 14:04:53 -0500 |
| commit | b8db6362ff5b5a102f02471c9984eba377de8391 (patch) | |
| tree | f523824556e8e53a92ca92c7bbbf51634ebeed2c /arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts | |
| parent | 16338e4fe9b03a812b4ab659992b614dc10c9bcc (diff) | |
MLK-23693-1: arm64: dts: imx8dxl: add nand support on ddr3 board
add the nand node to support nand in imx8dxl ddr3 evk board.
Signed-off-by: Han Xu <han.xu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts index 796f19a93dc8..8dd698dbbff1 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts @@ -306,6 +306,14 @@ status = "okay"; }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; + max-cs = <1>; +}; + &pcieb{ compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; pinctrl-names = "default"; @@ -525,6 +533,27 @@ >; }; + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + IMX8DXL_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c + + IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c + IMX8DXL_USDHC1_WP_CONN_NAND_ALE 0x0e00004c + IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + >; + }; + pinctrl_lpspi3: lpspi3grp { fsl,pins = < IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c |