diff options
| author | Fugang Duan <fugang.duan@nxp.com> | 2020-04-09 18:04:04 +0800 |
|---|---|---|
| committer | Fugang Duan <fugang.duan@nxp.com> | 2020-04-09 18:04:04 +0800 |
| commit | cbd935672b0f8561ddaf4affd6d8dab39fed3ed5 (patch) | |
| tree | b2eb38a51d8bd4eacccd36653bc0e4148f76e32e /arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | |
| parent | 29eda88da89e34ad792fff0872be4f1ba67e173c (diff) | |
MLK-23764 arm64: dts: imx8dxl: enable wireless support for evk board
Add extra pcie dts file to enable wireless (like NXP
88w8997 and CYPRESS 4356/4359) since most of A0 chips
pcie has issue, which is convenient for tester to verify
wireless on comming release with golden chips.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8dxl-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 29 |
1 files changed, 20 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index fa1ba07a623e..b739aefaab30 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -88,6 +88,14 @@ }; }; + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + reg_can0_stby: regulator-can0-stby { compatible = "regulator-fixed"; regulator-name = "can0-stby"; @@ -159,6 +167,7 @@ regulator-max-microvolt = <3300000>; regulator-name = "m2_uart1_sel"; gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; regulator-always-on; }; @@ -503,9 +512,10 @@ }; &lpuart1 { - pinctrl-names = "default"; - pinctrl-1 = <&pinctrl_lpuart1>; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; }; &flexcan2 { @@ -726,6 +736,7 @@ pinctrl_hog: hoggrp { fsl,pins = < IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c >; @@ -827,17 +838,17 @@ pinctrl_lpuart0: lpuart0grp { fsl,pins = < - IMX8DXL_UART0_RX_ADMA_UART0_RX 0x0600004c - IMX8DXL_UART0_TX_ADMA_UART0_TX 0x0600004c + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 >; }; pinctrl_lpuart1: lpuart1grp { fsl,pins = < - IMX8DXL_UART1_TX_ADMA_UART1_TX 0x0600004c - IMX8DXL_UART1_RX_ADMA_UART1_RX 0x0600004c - IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600004c - IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600004c + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 >; }; |