diff options
author | Teo Hall <teo.hall@nxp.com> | 2020-02-02 17:05:19 -0600 |
---|---|---|
committer | Anson Huang <Anson.Huang@nxp.com> | 2020-02-13 07:51:40 +0800 |
commit | dc329c155d09e496fba9f77611ecc5badf19e4be (patch) | |
tree | 3e800c3081c6b78c871e5fe3378bd357e20d6101 /arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi | |
parent | 711cce5436e319e88c2f27992431da4175652139 (diff) |
MLK-23273-5: arm64: dts: Add DT support for imx8dxl
Add DT support for i.MX8DXL.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi new file mode 100644 index 000000000000..107578e328be --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +&lsio_gpio0 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu0 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu1 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu2 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu3 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu4 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; +}; |