diff options
| author | Adrian Alonso <adrian.alonso@nxp.com> | 2020-08-17 14:33:24 -0500 |
|---|---|---|
| committer | Adrian Alonso <adrian.alonso@nxp.com> | 2020-08-19 09:03:43 -0500 |
| commit | 9b011c556080120eea271803cc4909cbb635f21c (patch) | |
| tree | a32ba9227d37b51b7afc8fb960b9ef19b58ebd6a /arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts | |
| parent | 26685b224401305756ef35858a9c7f83efb85846 (diff) | |
MLK-24512: dts: arm64: freescale: imx8mm ddr4 ab2 target support
Add support for imx8mm ddr4 audio board 2.0 target for
revision C and B; Include Cortex-M4 dts support
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts new file mode 100644 index 000000000000..b8ec04c4cdcc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-ab2.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + reg = <0 0x80000000 0 0x0101E400>; + no-map; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + leds { + panel { + status = "disabled"; + }; + }; + + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +&clk { + init-on-array = < + IMX8MM_CLK_UART4_ROOT + IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE + IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB + IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB + IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV + IMX8MM_ARM_PLL_OUT + >; +}; + +&i2c2 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; |