diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2019-09-25 14:42:34 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:58 +0800 |
| commit | 5643e0913def81943fe0076ef7363b88f6a2b691 (patch) | |
| tree | 23a9aee319f5de3b35d2c814c0e81b39a77c7f9f /arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts | |
| parent | a22e26b75ab0af2a8435e959b439ff73f6bebd77 (diff) | |
arm64: dts: imx8mm: Add imx8mm ddr4 evk board support
Add i.MX8MM DDR4 EVK board support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts new file mode 100644 index 000000000000..3e2df7f649e4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +/ { + model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; + + leds { + pinctrl-0 = <&pinctrl_gpio_led_2>; + + status { + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&iomuxc { + imx8mm-evk { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + + pinctrl_gpio_led_2: gpioled2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * DDR4 board is same to the RevB board, configure + * PCIe REFCLK to internal PLL. + */ +&pcie0{ + ext_osc = <0>; + status = "okay"; +}; |