diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2019-08-20 04:23:49 -0400 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:06:34 +0800 |
| commit | ea334b7f6404bbe239a84cebd6e2399939e31f66 (patch) | |
| tree | 3b3440ebb6118b6451213e43e0a3c17c4d93f56d /arch/arm64/boot/dts/freescale/imx8mm-evk.dts | |
| parent | 30aeb21a6ffbef955800f0fc04d4beeb683bba68 (diff) | |
ARM64: dts: enable pcie on imx8mm
Enable PCIe on iMX8MM platforms.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index a6d5cb0e72e6..c91367b3099b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -36,6 +36,12 @@ #reset-cells = <0>; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -104,6 +110,20 @@ }; }; +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + ext_osc = <1>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -448,6 +468,14 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + >; + }; + pinctrl_pmic: pmicirq { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 |