diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-09-09 13:33:50 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-09-10 09:12:36 +0200 |
| commit | a170cb00218bb56d86186fd5c06d311d9b87a531 (patch) | |
| tree | f3f35831630fd68cbb2c88f8949838260122d9a3 /arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | |
| parent | 8a4f1f74493ebc363330587bdb0cdb666e6714ac (diff) | |
arm64: dts: imx8mm-verdin/-dev: fix dsi mezzanine pinout
Fix dsi mezzanine pinout and group them Verdin MEZ_* pins together. The main
change involves the Verdin MEZ_DSI_1_INT pin available on SODIMM 17
either with pull-down as before used for the DSI to HDMI display adapter
where HPD is active-high vs. with pull-up for the DSI to LVDS
display adapter where the INT# is active-low open-drain.
Also MEZ_GPIO2 changed from a pull-down to a pull-up.
While at it also remove the spurious t from pintctrl_ctrl_sleep_moci and
the spurious new-line at the end of the carrier board device tree file.
Related-to: ELB-2691
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 64 |
1 files changed, 36 insertions, 28 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index d9f09c651ab6..b444d020829b 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -342,7 +342,7 @@ line-name = "CTRL_SLEEP_MOCI#"; output-high; pinctrl-names = "default"; - pinctrl-0 = <&pintctrl_ctrl_sleep_moci>; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; }; }; @@ -734,18 +734,12 @@ >; }; - pintctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4 /* CTRL_SLEEP_MOCI */ >; }; - pinctrl_dsi_bkl_en: dsi_bkl_en { - fsl,pins = < - MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */ - >; - }; - pinctrl_ecspi2: ecspi2grp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */ @@ -818,19 +812,6 @@ >; }; - /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */ - pinctrl_gpio1: gpio1grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */ - >; - }; - - pinctrl_gpio2: gpio2grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x184 /* SODIMM 208 */ - >; - }; - pinctrl_gpio3: gpio3grp { fsl,pins = < MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */ @@ -900,13 +881,6 @@ >; }; - /* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */ - pinctrl_gpio_hpd: gpiohpdgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */ - >; - }; - pinctrl_gpio_keys: gpiokeysgrp { fsl,pins = < MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1c4 /* SODIMM 252 */ @@ -945,6 +919,40 @@ >; }; + /* Verdin MEZ_DSI_1_BKL_EN */ + pinctrl_mez_dsi_1_bkl_en: mezdsi1bklengrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */ + >; + }; + + /* Verdin MEZ_DSI_1_INT HPD (pulled-down as active-high) */ + pinctrl_mez_dsi_1_int_hpd: mezdsi1inthpdgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */ + >; + }; + + /* Verdin MEZ_DSI_1_INT# (pulled-up as active-low) */ + pinctrl_mez_dsi_1_int_n: mezdsi1intngrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c4 /* SODIMM 17 */ + >; + }; + + /* MEZ_GPIO_1 shared with MEZ_DSI_1_INT on Verdin DSI to HDMI Display Adapter */ + pinctrl_mez_gpio1: mezgpio1grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */ + >; + }; + + pinctrl_mez_gpio2: mezgpio2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1c4 /* SODIMM 208 */ + >; + }; + pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6 /* SODIMM 244 */ |