diff options
author | Richard Zhu <hongxing.zhu@nxp.com> | 2019-11-13 16:20:57 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:09:55 +0800 |
commit | 3d56ae8d8343c4353499d64a62fecb60a81253ea (patch) | |
tree | cd12e115af9a1edf8ed5686debf54a92e9602e18 /arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts | |
parent | 09cbc6b4dd6ac965e6ef06318252336bf78ac0d2 (diff) |
arm64: dts: add the rpmsg and enable rpmsg audio on imx8mn
Enable the RPMSG on iMX8MN DDR4 EVK platform, and verify the rpmsg
audio feature.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts new file mode 100644 index 000000000000..de2e1d09a51d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m_core_reserved: m_core@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8000000 0 0x400000>; + }; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: audio-codec { + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mn-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "wm8524-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + }; +}; + +&clk { + init-on-array = < + IMX8MN_CLK_UART4_ROOT + >; +}; + +/* + * ATTENTION: M core may use IPs like below + * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1/3 and PDM + */ + +&ecspi2 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&pwm3 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + status = "okay"; +}; + +&sai3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&wdog1 { + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; |