diff options
| author | Robby Cai <robby.cai@nxp.com> | 2019-09-30 19:13:20 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:08:30 +0800 |
| commit | af572c4c9dbfd41cacc915c50bb986bedf9c4da9 (patch) | |
| tree | 5bb86682c96cfd5b535c3f37d5b33b5b2459685f /arch/arm64/boot/dts/freescale/imx8mq-evk.dts | |
| parent | a532ea77772448ada803e7e0dce80190b86dc239 (diff) | |
ARM64: dts: imx8mq-evk: enable csi bridge, mipi csi and mipi camera ov5640
enable csi bridge, mipi csi and mipi camera ov5640
Signed-off-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit 7f7bbb2dfb7a19381f1f6dab75110329b89dc05b)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq-evk.dts')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 134 |
1 files changed, 134 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 4a2f32b1706b..6b6a39c38607 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -181,6 +181,30 @@ cpu-supply = <&buck2_reg>; }; +&csi1_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + +&csi2_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + status = "okay"; + + port { + csi2_ep: endpoint { + remote-endpoint = <&csi2_mipi_ep>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -208,6 +232,40 @@ assigned-clock-rates = <0>, <0>, <786432000>, <722534400>; }; +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint@0 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + + csi1_mipi_ep: endpoint@1 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&mipi_csi_2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi2_sensor_ep: endpoint@0 { + remote-endpoint = <&ov5640_mipi2_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + + csi2_mipi_ep: endpoint@1 { + remote-endpoint = <&csi2_ep>; + }; + }; +}; + &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; @@ -305,6 +363,28 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + ov5640_mipi2: ov5640_mipi2@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + csi_id = <1>; + pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi2_ep: endpoint { + remote-endpoint = <&mipi2_sensor_ep>; + }; + }; + }; + pmic@8 { compatible = "fsl,pfuze100"; reg = <0x8>; @@ -469,6 +549,35 @@ }; }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; +}; + &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; @@ -629,6 +738,24 @@ }; + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + >; + }; + pinctrl_csi2_pwn: csi2_pwn_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -669,6 +796,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 + >; + }; + pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 |