diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2019-09-03 11:43:07 -0400 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:14 +0800 |
| commit | 009f3dbd0b6223b88917af974357d9249c8fcec8 (patch) | |
| tree | b8485530a53d0735c7b209fe2c03d40a70cccbe4 /arch/arm64/boot/dts/freescale/imx8mq-evk.dts | |
| parent | 8561ea399e4d0a1d95199722f016e1383475aab9 (diff) | |
arm64: dts: enable the second pcie on imx8mq evk board
Enable the second PCIe port on iMX8MQ EVK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq-evk.dts')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 0580cbb74ce0..d708d5311492 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -51,6 +51,12 @@ clock-frequency = <100000000>; }; + pcie1_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + ptn36043 { compatible = "nxp,ptn36043"; pinctrl-names = "default"; @@ -475,6 +481,19 @@ status = "okay"; }; +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; }; @@ -657,6 +676,14 @@ >; }; + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 /* open drain, pull up */ + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + pinctrl_qspi: qspigrp { fsl,pins = < MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 |