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authorLi Jun <jun.li@nxp.com>2019-01-27 22:35:13 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:03:59 +0800
commit01ea60eb25ea694ba169108a56e681484bbfb924 (patch)
tree2708def1bb2b7f9c1f367d2340b9c8ae3f4a58f5 /arch/arm64/boot/dts/freescale/imx8mq-evk.dts
parent9bef6e0c6125cd3ca30d3e7dfd6108893e0f82f2 (diff)
ARM64: dts: imx8mq-evk: add typec switch node
PTN36043 is a super speed active channel switch controlled by a GPIO, used for USB3 data channel switch according to typec orientation. Signed-off-by: Li Jun <jun.li@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq-evk.dts')
-rwxr-xr-xarch/arm64/boot/dts/freescale/imx8mq-evk.dts32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index b36f0808e1e5..b0a632b69802 100755
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -43,6 +43,20 @@
clock-frequency = <100000000>;
};
+ ptn36043 {
+ compatible = "nxp,ptn36043";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ss_sel>;
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ orientation-switch;
+
+ port {
+ usb3_data_ss: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
+ };
+
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
@@ -265,6 +279,18 @@
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ typec_con_ss: endpoint {
+ remote-endpoint = <&usb3_data_ss>;
+ };
+ };
+ };
};
};
};
@@ -437,6 +463,12 @@
>;
};
+ pinctrl_ss_sel: usb3ssgrp{
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
+ >;
+ };
+
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059