diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2021-03-09 14:46:53 +0800 |
|---|---|---|
| committer | Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> | 2021-04-27 10:42:02 +0000 |
| commit | 3d16eb4385844385488d16332980187eddb624aa (patch) | |
| tree | 46cf55252668635dd9744d5616f29af5361cafa9 /arch/arm64/boot/dts/freescale/imx8mq-evk.dts | |
| parent | 5cead2a105ad5c4d119f0dec36c1284e11a29039 (diff) | |
MLK-25333-1 arm64: dts: specify the clock rate and parent of pcie clocks
Specify the clock rate and parent of i.MX8MQ/MM PCIe clocks.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 5c9865f4184ad9251d147126814a36e193226aae)
(cherry picked from commit 768c144fca6f3ba4285e80e09e4aec803ffea1a7)
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq-evk.dts')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 30 |
1 files changed, 21 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index cd84f5679eee..616863fc2d31 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -662,9 +662,13 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; hard-wired = <1>; status = "okay"; }; @@ -679,9 +683,13 @@ <&clk IMX8MQ_CLK_PCIE2_PHY>, <&pcie1_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; status = "okay"; }; @@ -693,9 +701,13 @@ <&clk IMX8MQ_CLK_PCIE2_PHY>, <&pcie1_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; status = "disabled"; }; |