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authorPhilippe Schenker <philippe.schenker@toradex.com>2021-08-20 11:13:24 +0200
committerPhilippe Schenker <philippe.schenker@toradex.com>2021-09-07 09:47:41 +0200
commit75e357e5be10c9f3e76c5061dc999e54d6ffa893 (patch)
treef8c7d1b4bd278a2fbd2dc916072b8f0511bf88f9 /arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
parent5e9d9197e3f93faeeefbe7e00434e2a145810bc5 (diff)
ARM64: dts: apalis-imx8: leave pcie/sata clk enabled
remove clock gate that dynamically enabled disabled the sata clock also used for PCIe clock input on the SoC. It turned out that this approach leads to disable this clock during the boot process which in turn leads to some cases where wifi does not work after boot. Related-to: ELB-3534 Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi22
1 files changed, 15 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
index b77bc4dc0450..b102830ad461 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
@@ -9,10 +9,22 @@
model = "Toradex Apalis iMX8QM";
compatible = "toradex,apalis-imx8",
"fsl,imx8qm";
-};
-/delete-node/ &pcie_wifi_refclk;
-/delete-node/ &pcie_wifi_refclk_gate;
+ pcie_sata_refclk: sata-clock-generator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ pcie_sata_refclk_gate: sata-ref-clock {
+ compatible = "gpio-gate-clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
+ #clock-cells = <0>;
+ clocks = <&pcie_sata_refclk>;
+ enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_HIGH>;
+ };
+};
&ethphy0 {
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
@@ -323,10 +335,6 @@
>;
};
-&pcie_sata_refclk_gate {
- enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_HIGH>;
-};
-
/* On-module Wi-Fi */
&pcieb {
clocks = <&pcieb_lpcg 0>,