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authorPhilippe Schenker <philippe.schenker@toradex.com>2020-08-05 20:30:52 +0200
committerOleksandr Suvorov <oleksandr.suvorov@toradex.com>2021-01-27 20:36:42 +0200
commit795682b0ab9e82d327412a9481bd689ec31bff4e (patch)
tree0490fd5507957bb3da88c2a9af7a0e1fe3859b68 /arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
parent68f701763836773fee3b338c3d548602005e9257 (diff)
arm64: dts: apalis-imx8: initial devicetree
This commit holds the initial devicetrees for colibri-imx8 module. They are based on the devicetree from toradex_4.14-2.3.x-imx branch and contain only a stripped down subset of the features which compile and should act as a starting point for further bringup on this branch. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Conflicts: arch/arm64/boot/dts/freescale/Makefile Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi113
1 files changed, 113 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
new file mode 100644
index 000000000000..687f7c720462
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2017-2020 Toradex
+ */
+
+#include "imx8qm-apalis-v1.1.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX8QM";
+ compatible = "toradex,apalis-imx8qm", "fsl,imx8qm";
+};
+
+&ethphy0 {
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+};
+
+/* Apalis I2C2 (DDC) */
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c0>;
+};
+
+&pinctrl_fec1 {
+ fsl,pins = <
+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 1.8V mode */
+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
+ IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
+ IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
+ IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
+ IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
+ IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
+ IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
+ IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
+ IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
+ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
+ IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020
+ /* On-module ETH_RESET# */
+ IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020
+ /* On-module ETH_INT# */
+ IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000060
+ >;
+};
+
+&pinctrl_fec1_sleep {
+ fsl,pins = <
+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
+ IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040
+ IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040
+ IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040
+ IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040
+ IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040
+ IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040
+ IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040
+ IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040
+ IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040
+ IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040
+ IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040
+ IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040
+ IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040
+ IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040
+ IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040
+ IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040
+ IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000040
+ >;
+};
+
+&iomuxc {
+ apalis-imx8qm {
+ /* Apalis I2C2 (DDC) */
+ pinctrl_lpi2c0: lpi2c0grp {
+ fsl,pins = <
+ IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022
+ IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022
+ >;
+ };
+ };
+};
+
+/* On-module PCIe_CTRL0_CLKREQ */
+&pinctrl_pcie_sata_refclk {
+ fsl,pins = <
+ IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021
+ >;
+};
+
+/* Apalis MMC1 */
+&usdhc2 {
+ /*
+ * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates
+ * issues with certain SD cards, disable 1.8V signaling for now.
+ */
+ no-1-8-v;
+};
+
+/* Apalis SD1 */
+&usdhc3 {
+ /*
+ * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates
+ * issues with certain SD cards, disable 1.8V signaling for now.
+ */
+ no-1-8-v;
+};