diff options
| author | Fugang Duan <fugang.duan@nxp.com> | 2019-07-29 16:39:18 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:20 +0800 |
| commit | 4efe4cf2e1eec7b7bc42fce656f054b89e3bf17c (patch) | |
| tree | 67acc48dda2dfce8d5ab73a98e65a848aa75a338 /arch/arm64/boot/dts/freescale/imx8qm-mek.dts | |
| parent | 155046d3d7178f3e660720da53cc3b5bea116c67 (diff) | |
arm64: dts: imx8qm-mek: enable enet2 port
Add enet2 port enable for imx8qm MEK board.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-mek.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 0c505e005af2..01141d689388 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -98,6 +98,15 @@ }; + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "SD1_SPWR"; @@ -215,11 +224,12 @@ &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii-txid"; phy-handle = <ðphy0>; fsl,magic-packet; nvmem-cells = <&fec_mac0>; nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; status = "okay"; mdio { @@ -242,6 +252,19 @@ }; }; +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + status = "okay"; +}; + &pciea{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pciea>; @@ -465,6 +488,24 @@ >; }; + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + pinctrl_flexcan1: flexcan0grp { fsl,pins = < IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 |