diff options
| author | Clark Wang <xiaoning.wang@nxp.com> | 2019-07-30 15:44:30 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:24 +0800 |
| commit | 9493b7abaa9316951a85c21c6bc73f9dcd1a5b45 (patch) | |
| tree | 0cb4e8ace928dca913b5752715977bb0444fa358 /arch/arm64/boot/dts/freescale/imx8qm-mek.dts | |
| parent | 20341403d247902bdaed315594533c82d8077f46 (diff) | |
arm64: dts: add lpspi2 support for imx8qm-mek board
Enable LPSPI2 function on imx8qm-mek board. LPSPI2 pinout are on the
base board.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-mek.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 01141d689388..0cebce5a608b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -175,6 +175,22 @@ status = "okay"; }; +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; @@ -541,6 +557,21 @@ >; }; + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c + IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c + IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c + IMX8QM_SPI2_CS0_DMA_SPI2_CS0 0x0600004c + >; + }; + + pinctrl_lpspi2_cs: lpspi2cs { + fsl,pins = < + IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 + >; + }; + pinctrl_lpuart0: lpuart0grp { fsl,pins = < IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 |