diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-03-24 15:42:26 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-03-26 16:40:48 +0800 |
| commit | c24b099bb5ee5fd9f320a941362db04e9e42cb22 (patch) | |
| tree | 9c8e7d5a5c623195d495a1cc640cb20a9e95baf0 /arch/arm64/boot/dts/freescale/imx8qm-mek.dts | |
| parent | 7c1e5ff049544d319a7a70d4793a0f6b749e9d75 (diff) | |
MLK-23668-1 arm64: dts: imx8qm: add multi-pcie ports support
- Enable the PCIEB port on the i.MX8QM MEK and base board.
- In the PCIEAX1PCIEBx1SATA usecase, the PHYX2_PCLK[0] is mandatory
required by PCIEB. Otherwise PCIEB can't link up when exist from
L2 mode when only PCIEB is used.
- PCIEB has one more PER clock, since that the PCIEA CSR register
would be configuired when PCIEB is initialized.
- Regarding to the base board HW limitation(two Disable#) are not
connected. Only the standard PCIe EP device is supported on PCIEB port.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-mek.dts')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index f12932180482..5f8df11c49d7 100755 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -862,6 +862,14 @@ status = "okay"; }; +&pcieb{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + status = "okay"; +}; + &rpmsg0{ /* * 64K for one rpmsg instance: @@ -884,7 +892,7 @@ &sata { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-0 = <&pinctrl_sata>; clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>; ext_osc = <1>; status = "okay"; @@ -1442,7 +1450,6 @@ pinctrl_pciea: pcieagrp{ fsl,pins = < IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 - IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 >; @@ -1450,6 +1457,13 @@ pinctrl_pcieb: pciebgrp{ fsl,pins = < + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_sata: satagrp{ + fsl,pins = < IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 >; }; |