diff options
author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-03-24 15:43:19 +0800 |
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committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-03-26 16:40:48 +0800 |
commit | 7fb4da245bf9f414373180bd4009687fa24a53f4 (patch) | |
tree | ccc5f021b316f66c9090e1e342db33aa9486eadc /arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts | |
parent | 8c28614abfa0326fec30bea157da36f21b7818e5 (diff) |
MLK-23669 arm64: dts: imx8qm: add pcieax2pciebx1 usecase
Different HSIO usecase may be used by customers.
- add PCIEAx2PCIEBx1 usecase for example.
Only verified PCIA one lane refer to the iMX8QM MEK and Baseboard
hardware limitation.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts b/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts new file mode 100644 index 000000000000..22738c54673a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8qm-mek.dts" + +/* + * Add the PCIeA x2 lanes and PCIeB x1 lane usecase + * hsio-cfg = <PCIEAX2PCIEBX1> + * NOTE: In this case, the HSIO nodes contained + * hsio-cfg = <PCIEAX1PCIEBX1SATA> would be re-configured. + */ +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + num-lanes = <2>; + clocks = <&pciea_lpcg 0>, + <&pciea_lpcg 1>, + <&pciea_lpcg 2>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per","pcie_per", "misc_per"; + hsio-cfg = <PCIEAX2PCIEBX1>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx1_lpcg 0>, + <&phyx2_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "pcie_phy_pclk", "phy_per", + "pcie_per", "pciex2_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_SERDES_1>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_per", "pcie_phy", + "pcie_serdes", "hsio_gpio"; + hsio-cfg = <PCIEAX2PCIEBX1>; + status = "okay"; +}; + +&sata { + status = "disabled"; +}; |