diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2019-08-15 05:31:51 -0400 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:06:17 +0800 |
| commit | 22dc13a0e638b89fb7d7aded58a044aea2b15cb6 (patch) | |
| tree | 41899af66e0dbc0bead6c566ffcde507ca993532 /arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | |
| parent | d644f2ee4a48c6d8061c4a7ae67f6040868fe0e5 (diff) | |
arm64: dts: imx8: add the fixed hsio ref clocks
External 100Mhz differential OSC is used as HSIO REF clock source, so
set it as the parent clk of the PHY PCLK.
Then add the fixed HSIO REF clocks regarding the different HSIO use
cases.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index c0d4658c24d7..ece43350dadb 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -42,6 +42,20 @@ power-domains = <&pd IMX_SC_R_PCIE_A>; }; + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + phyx2_crr0_lpcg: clock-controller@5f0a0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f0a0000 0x10000>; |