diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-12-03 20:17:43 +0800 |
|---|---|---|
| committer | Liu Ying <victor.liu@nxp.com> | 2019-12-04 13:26:55 +0800 |
| commit | 545c6201daf46624a3834a7014971a6c32b2073d (patch) | |
| tree | a0321c5d8c05f79c8280ac913c4c87079c4ad8a8 /arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | |
| parent | 533604f38375f437cdf11ad79d048afb3e12096a (diff) | |
LF-95-1 arm64: imx8qm-ss-lvds.dtsi: Correct LVDS region address and size
The LVDS region is the CSR(Control Status Registers) space.
The spec tells us that the CSR start address is 0x1000 and end address
is 0x1FFF according to the subsystem start address. However, it turns
out some space are inaccessible, which would accidently cause system
hang via kernel regmap debugfs. This patch corrects the LVDS region
start address and chooses a sensible size, which makes sure all exposed
registers are accessible.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi index 1fe9afa12e03..b375bcf99f97 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi @@ -78,9 +78,9 @@ power-domains = <&pd IMX_SC_R_LVDS_0>; }; - lvds0_region: lvds_region@56240000 { + lvds0_region: lvds_region@56241000 { compatible = "syscon"; - reg = <0x56240000 0x10000>; + reg = <0x56241000 0xf0>; }; ldb1_phy: ldb_phy@56241000 { @@ -244,9 +244,9 @@ power-domains = <&pd IMX_SC_R_LVDS_1>; }; - lvds1_region: lvds_region@57240000 { + lvds1_region: lvds_region@57241000 { compatible = "syscon"; - reg = <0x57240000 0x10000>; + reg = <0x57241000 0xf0>; }; ldb2_phy: ldb_phy@57241000 { |